Field of the Invention
The present invention is directed in general to integrated circuit devices and methods for manufacturing same. In one aspect, the present invention relates to the manufacture and use of gallium nitride switch devices.
Description of the Related Art
Semiconductor devices used with high power applications, such as optoelectronic, high-power and high-frequency devices, operate at higher temperatures and work at much higher voltages than conventional transistors. To meet these operating requirements, high power semiconductor devices may be formed with semiconductor materials, such as Gallium nitride (GaN), having material properties that are suitable for use in such applications. For example, switch devices, such as MOSFET and MESFET transistors, formed with GaN based substrates offer many advantages in high power electronics, especially in automotive and electric car applications, by delivering high current, low resistance during an ON-state, but have unacceptable OFF-state gate and drain leakage currents, resulting in significant power consumption in the stand-by or reversed biased state. To illustrate the amount of leakage current, a 1 mA/mm level of OFF-state leakage will consume 60 watts for a 100 mm gate width device at a reverse bias of 600V. Devices that exhibit high leakage currents can have limited operating voltage and/or power density of the device (e.g., transistors), and typically have inferior, and oftentimes unacceptable, performance characteristics. Leakage current problems can be exacerbated with GaN based substrates which include a thick GaN epi layer and/or buffer layer (e.g., GaN/AlGaN/AlN) having defects and contaminants which provide an easy leakage current path in the devices. Attempts to reduce leakage current in such devices have used mesa isolation and implant isolation techniques which are implemented together in the fabrication process (e.g., prior to source/drain contact formation) in order to isolate thick buffer layers needed to provide strong OFF-state breakdown voltage protection, but this approach creates additional leakage current paths on the side wall of mesa and gate electrodes have to cross from low isolated regions to the elevated active regions of a device.
Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.